The next step of energy-driven computer architecture devoment: In- and near-memory computing

Abstract - The development in the last two decades on the computer architecture side was primarily driven by energy aspects. Of course, the primary goal was to provide more compute performance but since the end of Dennard scaling this was only achievable by reducing the energy requirements in processing, moving and storing of data. This leaded to the development from single-core to multi-core, many-core processors, and increased use of heterogeneous architectures in which multi-core CPUs are co-operating with specialized accelerator cores. The next in this development are near- and in-memory computing concepts, which reduce energy-intensive data movements. 

New non-volatile, so-called memristive, memory elements like Resistive RAMs (ReRAMs), Phase Change Memories (PCMs), Spin-torque Magnetic RAMS (STT-MRAMs) or devices with ferroelectric tunnel junctions (FTJs) play a decisive role in this context. They are not only predestined for low power reading but also for processing. In this sense they are devices which can be used in principle for storing and processing. Furthermore, such elements offer multi-bit capability that supports known but due to a so far lack of appropriate technology not realised ternary arithmetic. Furthermore, they are attractive for the use in low-power quantized neural networks. These benefits are opposed by difficulties in writing such elements expressed by low endurance and higher power requirements in writing compared to conventional SRAM or DRAM technology. 

These pro and cons have to be carefully weighed against each other during computer design. In the talk wil be presented corresponding architectures examples which were developed by the group of the author and in collaboration work with others. The result of this research brought, e.g. mixed-signal neuromorphic architectures as well as ternary compute circuits for future low-power near- and in-memory computing architectures.  

Biographie - Dietmar Fey hat an der Friedrich-Alexander Universität Erlangen-Nürnberg (FAU) Informatik studiert und dort auch auf dem Gebiet Optical Computing promoviert. An der Friedrich-Schiller-Universität Jena (FSU) wurde er im Fach Informatik 1999 habilitiert. Nach zweijähriger Tätigkeit als Privatdozent an der UniversitätSiegen wurde er an die FSU für eine C3-Professur "Technische Informatik" berufen. Seit 2009 leitet er den Lehrstuhl Rechnerarchitektur an der FAU. Seine Forschungsinteressen liegen auf dem Gebiet Memristives Rechnen, Parallele Eingebettete Systeme und Parallele Architekturen für Embedded High Performance Computing. Er ist Mitglied der GI, des GI/ITG-Fachausschusses ARCS (Architecture of Computing Systems) und des Europäischen Netzwerks HiPEAC (High Performance Embedded  Architectures and Compilers).